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2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Edmonton, Canada
Aug. 23, 2014 to Aug. 27, 2014
ISBN: 978-1-5090-6607-0
pp: 237-249
Andrew Lukefahr , Advanced Computer Architecture Laboratory, Ann Arbor, MI, USA
Shruti Padmanabha , Advanced Computer Architecture Laboratory, Ann Arbor, MI, USA
Reetuparna Das , Advanced Computer Architecture Laboratory, Ann Arbor, MI, USA
Ronald Dreslinski , Advanced Computer Architecture Laboratory, Ann Arbor, MI, USA
Thomas F. Wenisch , Advanced Computer Architecture Laboratory, Ann Arbor, MI, USA
Scott Mahlke , Advanced Computer Architecture Laboratory, Ann Arbor, MI, USA
ABSTRACT
Heterogeneous architectures offer many potential avenues for improving energy efficiency in today's low-power cores. Two common approaches are dynamic voltage/frequency scaling (DVFS) and heterogeneous microarchitectures (HMs). Traditionally both approaches have incurred large switching overheads, which limit their applicability to coarse-grain program phases. However, recent research has demonstrated low-overhead mechanisms that enable switching at granularities as low as 1K instructions. The question remains, in this fine-grained switching regime, which form of heterogeneity offers better energy efficiency for a given level of performance? The effectiveness of these techniques depend critically on both efficient architectural implementation and accurate scheduling to maximize energy efficiency for a given level of performance. Therefore, we develop PaTH, an offline analysis tool, to compute (near-)optimal schedules, allowing us to determine Pareto-optimal energy savings for a given architecture. We leverage PaTH to study the potential energy efficiency of fine-grained DVFS and HMs, as well as a hybrid approach. We show that HMs achieve higher energy savings than DVFS for a given level of performance. While at a coarse granularity the combination of DVFS and HMs still proves beneficial, for fine-grained scheduling their combination makes little sense as HMs alone provide the bulk of the energy efficiency.
INDEX TERMS
Switches, Multicore processing, Optimal scheduling, Voltage control, Schedules, Microarchitecture,Energy Efficiency, Heterogeneous Multicores, DVFS, Fine-Grained Architectures
CITATION
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald Dreslinski, Thomas F. Wenisch, Scott Mahlke, "Heterogeneous microarchitectures trump voltage scaling for low-power cores", 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), vol. 00, no. , pp. 237-249, 2014, doi:10.1145/2628071.2628078
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