2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Aug. 23, 2014 to Aug. 27, 2014
Irina Calciu , Brown University, Providence, RI, USA
Justin Gottschlich , Intel Labs, Santa Clara, CA, USA
Tatiana Shpeisman , Intel Labs, Santa Clara, CA, USA
Maurice Herlihy , Brown University, Providence, RI, USA
Gilles Pokam , Intel Labs, Santa Clara, CA, USA
The Intel Haswell processor includes restricted transactional memory (RTM), which is the first commodity-based hardware transactional memory (HTM) to become publicly available. However, like other real HTMs, such as IBM's Blue Gene/Q, Haswell's RTM is best-effort, meaning it provides no transactional forward progress guarantees. Because of this, a software fallback system must be used in conjunction with Haswell's RTM to ensure transactional programs execute to completion. To complicate matters, Haswell does not provide escape actions. Without escape actions, non-transactional instructions cannot be executed within the context of a hardware transaction, thereby restricting the ways in which a software fallback can interact with the HTM. As such, the challenge of creating a scalable hybrid TM (HyTM) that uses Haswell's RTM and a software TM (STM) fallback is exacerbated. In this paper, we present Invyswell, a novel HyTM that exploits the benefits and manages the limitations of Haswell's RTM. After describing Invyswell's design, we show that it outperforms NOrec, a state-of-the-art STM, by 35%, Hybrid NOrec, NOrec's hybrid implementation, by 18%, and Haswell's hardware-only lock elision by 25% across all STAMP benchmarks.
Hardware, Benchmark testing, Throughput, Synchronization, Instruction sets, Programming
I. Calciu, J. Gottschlich, T. Shpeisman, M. Herlihy and G. Pokam, "Invyswell: A hybrid transactional memory for Haswell's restricted transactional memory," 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), Edmonton, Canada, 2014, pp. 187-199.