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2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Edmonton, Canada
Aug. 23, 2014 to Aug. 27, 2014
ISBN: 978-1-5090-6607-0
pp: 3-14
Nuno Diegues , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa
Paolo Romano , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa
Luis Rodrigues , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa
ABSTRACT
Over the last years Transactional Memory (TM) gained growing popularity as a simpler, attractive alternative to classic lock-based synchronization schemes. Recently, the TM landscape has been profoundly changed by the integration of Hardware TM (HTM) in Intel commodity processors, raising a number of questions on the future of TM. We seek answers to these questions by conducting the largest study on TM to date, comparing different locking techniques, hardware and software TMs, as well as different combinations of these mechanisms, from the dual perspective of performance and power consumption. Our study sheds a mix of light and shadows on currently available commodity HTM: on one hand, we identify workloads in which HTM clearly outperforms any alternative synchronization mechanism; on the other hand, we show that current HTM implementations suffer of restrictions that narrow the scope in which these can be more effective than state of the art software solutions. Thanks to the results of our study, we identify a number of compelling research problems in the areas of TM design, compilers and self-tuning.
INDEX TERMS
Hardware, Synchronization, Program processors, Instruments, Programming, Power demand
CITATION
Nuno Diegues, Paolo Romano, Luis Rodrigues, "Virtues and limitations of commodity hardware transactional memory", 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), vol. 00, no. , pp. 3-14, 2014, doi:10.1145/2628071.2628080
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