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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 411
Ali Mustafa Zaidi , Computer Laboratory, University of Cambridge, CB3 0FD, UK
ABSTRACT
Compared to LegUp, an existing HLS tool [2], the VSFG exploits dynamic execution scheduling, speculation, and loop unrolling to achieve significant performance improvements (Figure 1), approaching or even exceeding a Nehalem Core i7 in some cases (not shown). Due to the overheads of speculation and loop unrolling, the energy cost incurred is 3× more than that of LegUp on average, but it is still only 0.25× of that for even a simple in-order Nios II/f processor (Figure 2).
INDEX TERMS
Instruction Level Parallelism, Dark Silicon, Dataflow, High-level Synthesis
CITATION
Ali Mustafa Zaidi, "Exposing ILP in custom hardware with a dataflow compiler IR", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 411, 2013, doi:10.1109/PACT.2013.6618841
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