Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
Ali Mustafa Zaidi , Computer Laboratory, University of Cambridge, CB3 0FD, UK
Compared to LegUp, an existing HLS tool , the VSFG exploits dynamic execution scheduling, speculation, and loop unrolling to achieve significant performance improvements (Figure 1), approaching or even exceeding a Nehalem Core i7 in some cases (not shown). Due to the overheads of speculation and loop unrolling, the energy cost incurred is 3× more than that of LegUp on average, but it is still only 0.25× of that for even a simple in-order Nios II/f processor (Figure 2).
Instruction Level Parallelism, Dark Silicon, Dataflow, High-level Synthesis
A. M. Zaidi, "Exposing ILP in custom hardware with a dataflow compiler IR," Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques(PACT), Edinburgh, United Kingdom United Kingdom, 2013, pp. 411.