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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 407
Joan J. Valls , Department of Computer Engineering, Universitat Politècnica de València (Spain)
Alberto Ros , Dept. de Ingeniería y Tecnología de Computadores, Universidad de Murcia (Spain)
Julio Sahuquillo , Department of Computer Engineering, Universitat Politècnica de València (Spain)
Maria E. Gomez , Department of Computer Engineering, Universitat Politècnica de València (Spain)
ABSTRACT
As silicon resources become increasingly abundant, core counts grow rapidly in successive chip-multiprocessors (CMP) generations. Parallel workloads represent an important segment for current and future CMPs mainly when many-core processors are considered. Unlike multiprogrammed workloads, the accessed blocks in these workloads can be classified in two categories: private, accessed only by one core, and shared, accessed by several cores. This paper takes advantage of this classification to access only a subset of the ways on each L1 cache access, thus reducing dynamic power consumption.
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CITATION
Joan J. Valls, Alberto Ros, Julio Sahuquillo, Maria E. Gomez, "PS-cache: An energy-efficient cache design for chip multiprocessors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 407, 2013, doi:10.1109/PACT.2013.6618839
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