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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 405
Thomas Grass , Universitat Politècnica de Catalunya (BarcelonaTech) and Barcelona Supercomputing Center, 08034, Spain
ABSTRACT
Chip Multi-Processors (CMPs) are evolving towards ever increasing core counts. Task-based programming models are a promising candidate for exploiting the parallelism offered by these machines. Simulation, the prevailing design methodology in computer architecture, is prohibitively time consuming, when it comes to CMPs featuring 1000s of cores. Sampled simulation [1], [2] is a standard technique for reducing simulation time for single-threaded architectures. Recently, these techniques have been extended to allow for simulation of multi-threaded systems [3]. However, they have not been assessed for dynamically scheduled multi-threaded programs.
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CITATION
Thomas Grass, "Task sampling: Computer architecture simulation in the many-core era", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 405, 2013, doi:10.1109/PACT.2013.6618838
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