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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 399
Biswabandan Panda , Dept. of CSE, Indian Institute of Technology, Madras, India
Shankar Balachandran , Dept. of CSE, Indian Institute of Technology, Madras, India
ABSTRACT
A single parallel application running on a multicore system shows sub-linear speedup because of slow progress of one or more threads known as critical threads. Identifying critical threads and accelerating them can improve system performance. One of the metrics that correlate to thread criticality is the number of cache misses and the penalty associated with it. This paper proposes a throttling mechanism called TCPT which throttles hardware prefetchers by changing the prefetch degree based on the thread criticality.
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CITATION
Biswabandan Panda, Shankar Balachandran, "TCPT - Thread criticality-driven prefetcher throttling", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 399, 2013, doi:10.1109/PACT.2013.6618835
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