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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 235-244
Wei Ding , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Jun Liu , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Mahmut Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Mary Jane Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
ABSTRACT
Optimizing cache locality has always been important since the emergence of caches, and numerous cache locality optimization schemes have been published in compiler literature. However, in modern architectures, cache locality is not the only factor that determines memory system performance. Many emerging multicores employ banked memory systems and each bank is attached a row-buffer that holds the most-recently accessed memory row (page). A last-level cache miss that also misses in the row-buffer can experience much higher latency than a cache miss that hits in the row-buffer. Consequently, optimizing for row-buffer locality can be as important as optimizing for cache locality. Targeting emerging multicores and multithreaded applications, this paper presents a compiler-directed row-buffer locality optimization strategy. This strategy modifies the memory layout of data to increase the number of row-buffer hits without increasing the number of misses in the on-chip cache hierarchy. We implemented our proposed optimization strategy in an open-source compiler and tested its effectiveness in improving the row-buffer performance using a set of multithreaded applications. Our results indicate that the proposed approach improves the average data access latency by about 29%, and this translates, on average, to about 15% improvement in execution time.
INDEX TERMS
Arrays, Layout, Optimization, Multicore processing, Vectors, Instruction sets, Indexes,transmission line, network-on-chip, traffic steering
CITATION
Wei Ding, Jun Liu, Mahmut Kandemir, Mary Jane Irwin, "Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 235-244, 2013, doi:10.1109/PACT.2013.6618820
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