Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
Nathan Beckmann , Massachusetts Inst. of Technol., Cambridge, MA, USA
Daniel Sanchez , Massachusetts Inst. of Technol., Cambridge, MA, USA
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two fundamental limitations. First, the latency and energy of shared caches degrade as the system scales up. Second, when multiple workloads share the CMP, they suffer from interference in shared cache accesses. Unfortunately, prior research addressing one issue either ignores or worsens the other: NUCA techniques reduce access latency but are prone to hotspots and interference, and cache partitioning techniques only provide isolation but do not reduce access latency.
Software, Hardware, Monitoring, Interference, Runtime, Quality of service, Coherence
N. Beckmann and D. Sanchez, "Meeting midway: improving CMP performance with memory-side prefetching," Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques(PACT), Edinburgh, United Kingdom United Kingdom, 2013, pp. 213-224.