Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
Augusto Vega , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Alper Buyuktosunoglu , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Pradip Bose , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
In Simultaneous Multi-Threading (SMT) chip multiprocessors (CMPs), thread placement is performed today in a largely power-unaware manner. For example, consolidation of active threads into fewer cores exposes opportunities for power savings that have not been addressed in prior work. The savings opportunity is especially high in the emerging context where percore power gating (PCPG) is becoming viable. The use of the optimum combination of core-wise SMT level and number of active cores to achieve a desired power-performance efficiency is a knob which has not been explored in prior work nor implemented as part of the operating system task scheduler.
Hardware, Instruction sets
A. Vega, A. Buyuktosunoglu and P. Bose, "Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems," Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques(PACT), Edinburgh, United Kingdom United Kingdom, 2013, pp. 167-176.