Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
Sandeep Navada , CPU Design Center, Qualcomm, Raleigh, NC, USA
Niket K. Choudhary , CPU Design Center, Qualcomm, Raleigh, NC, USA
Salil V. Wadhavkar , CPU Design Center, Qualcomm, Raleigh, NC, USA
Eric Rotenberg , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
A single-ISA heterogeneous chip multiprocessor (HCMP) is an attractive substrate to improve single-thread performance and energy efficiency in the dark silicon era. We consider HCMPs comprised of non-monotonic core types where each core type is performance-optimized to different instruction-level behavior and hence cannot be ranked - different program phases achieve their highest performance on different cores. Although non-monotonic heterogeneous designs offer higher performance potential than either monotonic heterogeneous designs or homogeneous designs, steering applications to the best-performing core is challenging due to performance ambiguity of core types.
Radiation detectors, Clocks, Multicore processing, Algorithm design and analysis, Genetic algorithms, Microarchitecture, Pipelines
S. Navada, N. K. Choudhary, S. V. Wadhavkar and E. Rotenberg, "Jigsaw: scalable software-defined caches," Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques(PACT), Edinburgh, United Kingdom United Kingdom, 2013, pp. 133-144.