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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 123-132
Josue Feliu , Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Val`encia, Spain
Julio Sahuquillo , Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Val`encia, Spain
Salvador Petit , Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Val`encia, Spain
Jose Duato , Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Val`encia, Spain
ABSTRACT
Improving the utilization of shared resources is a key issue to increase performance in SMT processors. Recent work has focused on resource sharing policies to enhance the processor performance, but their proposals mainly concentrate on novel hardware mechanisms that adapt to the dynamic resource requirements of the running threads. This work addresses the L1 cache bandwidth problem in SMT processors experimentally on real hardware. Unlike previous work, this paper concentrates on thread allocation, by selecting the proper pair of co-runners to be launched to the same core. The relation between L1 bandwidth requirements of each benchmark and its performance (IPC) is analyzed. We found that for individual benchmarks, performance is strongly connected to L1 bandwidth consumption, and this observation remains valid when several co-runners are launched to the same SMT core. Based on these findings we propose two L1 bandwidth aware thread to core (t2c) allocation policies, namely Static and Dynamic t2c allocation, respectively. The aim of these policies is to properly balance L1 bandwidth requirements of the running threads among the processor cores. Experiments on a Xeon E5645 processor show that the proposed policies significantly improve the performance of the Linux OS kernel regardless the number of cores considered.
INDEX TERMS
Bandwidth, Benchmark testing, Resource management, Program processors, Message systems, Multicore processing, Market research
CITATION
Josue Feliu, Julio Sahuquillo, Salvador Petit, Jose Duato, , , "An empirical model for predicting cross-core performance interference on multicore processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 123-132, 2013, doi:10.1109/PACT.2013.6618810
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