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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 93-102
Bin Wang , Auburn Univ., Auburn, AL, USA
Bo Wu , Coll. of William & Mary, Williamsburg, VA, USA
Dong Li , Oak Ridge Nat. Lab., Oak Ridge, TN, USA
Xipeng Shen , Coll. of William & Mary, Williamsburg, VA, USA
Weikuan Yu , Auburn Univ., Auburn, AL, USA
Yizheng Jiao , Auburn Univ., Auburn, AL, USA
Jeffrey S. Vetter , Oak Ridge Nat. Lab., Oak Ridge, TN, USA
ABSTRACT
Hybrid memory designs, such as DRAM plus Phase Change Memory (PCM), have shown some promise for alleviating power and density issues faced by traditional memory systems. But previous studies have concentrated on CPU systems with a modest level of parallelism. This work studies the problem in a massively parallel setting. Specifically, it investigates the special implications to hybrid memory imposed by the massive parallelism in GPU. It empirically shows that, contrary to promising results demonstrated for CPU, previous designs of PCM-based hybrid memory result in significant degradation to the energy efficiency of GPU. It reveals that the fundamental reason comes from a multi-facet mismatch between those designs and the massive parallelism in GPU. It presents a solution that centers around a close cooperation between compiler-directed data placement and hardware-assisted runtime adaptation. The co-design approach helps tap into the full potential of hybrid memory for GPU without requiring dramatic hardware changes over previous designs, yielding 6% and 49% energy saving on average compared to pure DRAM and pure PCM respectively, and keeping performance loss less than 2%.
INDEX TERMS
Graphics processing units, Phase change materials, Random access memory, Kernel, Parallel processing, Runtime, Hardware,software-hardware interface, chip multiprocessors, power management
CITATION
Bin Wang, Bo Wu, Dong Li, Xipeng Shen, Weikuan Yu, Yizheng Jiao, Jeffrey S. Vetter, "SMT-centric power-aware thread placement in chip multiprocessors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 93-102, 2013, doi:10.1109/PACT.2013.6618807
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