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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2013)
Edinburgh, United Kingdom United Kingdom
Sept. 7, 2013 to Sept. 11, 2013
ISSN: 1089-795X
ISBN: 978-1-4799-1018-2
pp: 51-61
Hiroshi Sasaki , Kyushu Univ., Fukuoka, Japan
Satoshi Imamura , Kyushu Univ., Fukuoka, Japan
Koji Inoue , Kyushu Univ., Fukuoka, Japan
ABSTRACT
Optimizing the performance in multiprogrammed environments, especially for workloads composed of multi-threaded programs is a desired feature of runtime management system in future manycore processors. At the same time, power capping capability is required in order to improve the reliability of microprocessor chips while reducing the costs of power supply and thermal budgeting. This paper presents a sophisticated runtime coordinated power-performance management system called C-3PO, which optimizes the performance of manycore processors under a power constraint by controlling two software knobs: thread packing, and dynamic voltage and frequency scaling (DVFS). The proposed solution distributes the power budget to each program by controlling the workload threads to be executed with appropriate number of cores and operating frequency. The power budget is distributed carefully in different forms (number of allocated cores or operating frequency) depending on the power-performance characteristics of the workload so that each program can effectively convert the power into performance. The proposed system is based on a heuristic algorithm which relies on runtime prediction of power and performance via hardware performance monitoring units. Empirical results on a 64-core platform show that C-3PO well outperforms traditional counterparts across various PARSEC workload mixes.
INDEX TERMS
Program processors, Power demand, Runtime, Optimization, Radio spectrum management, Linux, Mathematical model
CITATION
Hiroshi Sasaki, Satoshi Imamura, Koji Inoue, , "L1-bandwidth aware thread allocation in multicore SMT processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 51-61, 2013, doi:10.1109/PACT.2013.6618803
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