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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
ISBN: 978-1-5090-6609-4
pp: 481
Raghavendra K , PACE Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai-36, India
Tripti S Warrier , PACE Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai-36, India
Madhu Mutyam , PACE Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai-36, India
ABSTRACT
It is common for computers to have multi-level caches. This piece of work revolves around one question: Are all levels needed by all applications during all phases of their execution?, especially in the multi programmed scenario where giving the entire cache to one application and depriving the other might actually increase the performance.
INDEX TERMS
Benchmark testing, Computer science, Computers, Cache memory, Switches, Monitoring, Optimization,Miss rate, Cache
CITATION
Raghavendra K , Tripti S Warrier, Madhu Mutyam, "SkipCache: Miss-rate aware cache management", 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 481, 2012, doi:
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