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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
ISBN: 978-1-5090-6609-4
pp: 459-460
Rakesh Kumar , Dept. of Computer Architecture, Universitat Politècnica de Catalunya, 08034 Barcelona, Spain
Alejandro Martinez , Intel Barcelona Research Center, Intel Labs, 08034, BSpain
Antonio Gonzalez , Dept. of Computer Architecture, Universitat Politècnica de Catalunya, 08034 Barcelona, Spain
ABSTRACT
Hardware/Software (HW/SW) co-designed processors have emerged as a promising solution to the power and complexity problems of modern microprocessors. These processors utilize dynamic optimizations to improve the performance. However, vectorization, one of the most potent optimizations, has not yet received the deserved attention. This paper presents a speculative dynamic vectorization algorithm to explore its potential.
INDEX TERMS
Heuristic algorithms, Registers, Program processors, Optimization, Software algorithms, Benchmark testing, Computer architecture
CITATION
Rakesh Kumar, Alejandro Martinez, Antonio Gonzalez, "Speculative dynamic vectorization for HW/SW codesigned processors", 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 459-460, 2012, doi:
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