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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
ISBN: 978-1-5090-6609-4
pp: 455-456
Reetuparna Das , University of Michigan, USA
Rachata Ausavarungnirun , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
Akhilesh Kumar , Intel Labs, USA
Mani Azimi , Intel Labs, USA
ABSTRACT
How applications running on a many-core system are mapped to cores largely determines the interference between these applications in critical shared resources. This paper proposes application-to-core mapping policies to improve system performance by reducing inter-application interference in the on-chip network and memory controllers. The major new ideas of our policies are to: 1) map network-latency-sensitive applications to separate parts of the network from network-bandwidth-intensive applications such that the former can make fast progress without heavy interference from the latter, 2) map those applications that benefit more from being closer to the memory controllers close to these resources. Our evaluations show that both ideas significantly improve system throughput, fairness and interconnect power efficiency.
INDEX TERMS
Interference, System performance, System-on-chip, Multicore processing, Writing, Clocks, Scheduling,memory, Multicore, scheduling, interconnect
CITATION
Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi, "Application-to-core mapping policies to reduce memory interference in multi-core systems", 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 455-456, 2012, doi:
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