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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
ISBN: 978-1-5090-6609-4
pp: 449-450
Ping Xiang , Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, USA
Yi Yang , Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, USA
Mike Mantor , Graphics Products Group, AMD Inc., Orlando, FL, USA
Norm Rubin , Graphics Products Group, AMD Inc., Orlando, FL, USA
Huiyang Zhou , Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, USA
INDEX TERMS
Pipelines, Graphics processing units, Computer architecture, Hazards, Registers, Instruction sets, Parallel processing,Energy, GPGPU, Heterogeneous, ILP
CITATION
Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou, "Many-thread aware instruction-level parallelism: Architecting shader cores for GPU computing", 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 449-450, 2012, doi:
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