2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/
Nachiappan Chidambaram Nachiappan , The Pennsylvania State University, USA
Asit K. Mishra , Intel Corp., USA
Mahmut Kandemir , The Pennsylvania State University, USA
Anand Sivasubramaniam , The Pennsylvania State University, USA
Onur Mutlu , Carnegie Mellon University, USA
Chita R. Das , The Pennsylvania State University, USA
Data prefetching is an effective technique for hiding memory latency. When issued prefetches are inaccurate, performance can degrade. Prior research provided solutions to deal with inaccurate prefetches at the cache and memory levels, but not in the interconnect of a large-scale multiprocessor system. This work introduces application-aware prefetch prioritization techniques to mitigate the negative effects of prefetching in a network-on-chip (NoC) based multicore system. The idea is to rank prefetches from different applications based on their potential utility for the application and propensity to cause interference to other applications. Our evaluation shows that this approach provides significant performance improvements over a baseline that does not distinguish between prefetches from different applications.
Prefetching, System-on-chip, Multicore processing, System performance, Interference, Bandwidth, Delays
N. C. Nachiappan, A. K. Mishra, M. Kandemir, A. Sivasubramaniam, O. Mutlu and C. R. Das, "Application-aware prefetch prioritization in on-chip networks," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, USA, 2012, pp. 441-442.