2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/
Lihang Zhao , Information Sciences Institute, University of Southern California, Marina del Rey, 90242, USA
Woojin Choi , Information Sciences Institute, University of Southern California, Marina del Rey, 90242, USA
Jeff Draper , Information Sciences Institute, University of Southern California, Marina del Rey, 90242, USA
Hardware Transactional Memory (HTM) designs must implement conflict detection to guarantee the correctness of transaction execution. A conflict occurs when more than one transaction access the same data and at least one of them attempts to modify the data. The corresponding conflict detection mechanism usually works at a cacheline level that fits naturally into the cache coherence protocol. Thus, the inter-transaction communication for conflict detection is usually mapped onto the coherence communication controlled by the directory-based coherence protocols. In this paper, we identify inefficiency introduced by such mappings. The net effect of such inefficiency is excessive on-chip network traffic that consumes substantial dynamic power as packets are switched over the routers and links. We present TMNOC, a HTM and Network-on-Chip (NoC) co-design to improve network energy efficiency. The on-chip network, instead of a passive communication substrate, proactively filters out transactional requests that waste energy yet having no contribution to the progress of transactions. Experiment results show that TMNOC reduces energy consumption of the on-chip network by 14.5% on average (up to 38%) across a wide range of transaction applications.
System-on-chip, Coherence, Hardware, Routing protocols, Energy consumption, Microarchitecture
L. Zhao, W. Choi and J. Draper, "TMNOC: A case of HTM and NoC Co-design for increased energy efficiency and concurrency," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, USA, 2012, pp. 439-440.