2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/
Nilanjan Goswami , University of Florida, Gainesville, USA
Zhongqi Li , University of Florida, Gainesville, USA
Ajit Verma , University of Florida, Gainesville, USA
Ramkumar Shankar , University of Florida, Gainesville, USA
Tao Li , University of Florida, Gainesville, USA
As high-performance computing device, the GPU has exposed bandwidth and latency bottlenecks in on-chip interconnect and off-chip memory access. To eliminate such bottlenecks, we employ silicon nanophotonics and 3D stacking technologies in GPU microarchitecture. This provides higher communication bandwidth and lower latency signaling mechanisms at reduced power. Furthermore, to insulate the performance of the GPU compute cores from the interconnect bottlenecks we propose a novel interconnect aware thread scheduling scheme to alleviate the traffic congestion. We evaluate a 3D stacked GPU with 2048 SIMD cores having photonic interconnect. The photonic multiple-write-single-read crossbar network with 32B channel bandwidth on average, achieves 96% power reduction. We anticipate that for emerging workloads and microarchitectures the implications of the proposed ideas are far reaching in terms of power and performance.
Optical waveguides, Graphics processing units, Instruction sets, Optical interconnections, Bandwidth, System-on-chip, Silicon
N. Goswami, Zhongqi Li, A. Verma, R. Shankar and Tao Li, "Integrating nanophotonics in GPU microarchitecture," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, USA, 2012, pp. 425-426.