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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
ISBN: 978-1-5090-6609-4
pp: 421-422
Cheng Li , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843-3128, USA
Mark Browning , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843-3128, USA
Paul V. Gratz , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843-3128, USA
Samuel Palermo , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843-3128, USA
ABSTRACT
Achieving scaling performance as core counts increase to the hundreds in future chip-multi-processors (CMPs) requires high performing, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50% lower latency at low loads and 40% higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies 40% versus an electrical 2D mesh NoCs on the PARSEC shared memory, multithreaded benchmark suite.
INDEX TERMS
Photonics, Bandwidth, Throughput, Waveguide lasers, Optical waveguides, Power lasers, Ring lasers,Power Efficiency, CMP, NoC, Synthetic/Realistic Workload
CITATION
Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo, "LumiNOC: A power-efficient, high-performance, photonic network-on-chip for future parallel architectures", 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 421-422, 2012, doi:
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