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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
ISBN: 978-1-5090-6609-4
pp: 377-388
Gennady Pekhimenko , Carnegie Mellon University, USA
Vivek Seshadri , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
Michael A. Kozuch , Intel Labs Pittsburgh, USA
Phillip B. Gibbons , Intel Labs Pittsburgh, USA
Todd C. Mowry , Carnegie Mellon University, USA
ABSTRACT
Cache compression is a promising technique to increase on-chip cache capacity and to decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known compression algorithms (usually implemented in software) leads to high hardware complexity and unacceptable decompression/compression latencies, which in turn can negatively affect performance. Hence, there is a need for a simple yet efficient compression technique that can effectively compress common in-cache data patterns, and has minimal effect on cache access latency.
INDEX TERMS
Data compression, System-on-chip, Complexity theory, Hardware, Dynamic range, Compression algorithms, Bandwidth,Memory, Cache compression, Caching
CITATION
Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, Todd C. Mowry, "Base-delta-immediate compression: Practical data compression for on-chip caches", 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 377-388, 2012, doi:
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