2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/
Justin E. Gottschlich , Intel Corporation, Programming Systems Lab, USA
Maurice P. Herlihy , Brown University, Dept. of Computer Science, Canada
Gilles A. Pokam , Intel Corporation, Programming Systems Lab, USA
Jeremy G. Siek , University of Colorado-Boulder, Dept. of Electrical and Computer Engineering, USA
This paper presents TMProf, a transactional memory (TM) profiler, based on three visualization principles. These principles are (i) the precise graphical representation of transaction interactions including cross-correlated information and source code, (ii) visualized soft real-time playback of concurrently executing transactions, and (iii) dynamic visualizations of multiple executions. We describe how these principles break new ground and create new challenges for TM profilers. We discuss our experience using TMProf with InvalSTM, a state-of-the-art software TM, and show how TMProf's feedback led to the design of two new contention managers (CMs). We demonstrate the performance benefits of these CMs, which generally led to improved performance as the amount of work and threads increase per benchmark. Our experimental results show that iBalanced, one of our newly designed CMs, can increase transaction throughput by nearly 10× over iFair, InvalSTM's previously best performing CM.
Image color analysis, Visualization, Measurement, Real-time systems, Data visualization, Programming, Benchmark testing
J. E. Gottschlich, M. P. Herlihy, G. A. Pokam and J. G. Siek, "Visualizing transactional memory," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, USA, 2012, pp. 159-170.