2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/
Victor Jimenez , Barcelona Supercomputing Center, Spain
Roberto Gioiosa , Pacific Northwest National Laboratory, Richland, WA, USA
Francisco J. Cazorla , Spanish National Research, Council and Barcelona, Supercomputing Center, Spain
Alper Buyuktosunoglu , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Pradip Bose , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Francis P. O'Connell , IBM Systems and Technology Group, Austin, TX, USA
Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow the user to change some of their parameters. The prefetcher, however, is usually enabled in a default configuration during system bring-up and dynamic reconfiguration of the prefetch engine is not an autonomic feature of current machines. Conceptually, however, it is easy to infer that commonly used prefetch algorithms, when applied in a fixed mode will not help performance in many cases. In fact, they may actually degrade performance due to useless bus bandwidth consumption and cache pollution. In this paper, we present an adaptive prefetch scheme that dynamically modifies the prefetch settings in order to adapt to the workload requirements. We implement and evaluate adaptive prefetching in the context of an existing, commercial processor, namely the IBM POWER7. Our adaptive prefetch mechanism improves performance with respect to the default prefetch setting up to 2.7X and 30% for single-threaded and multiprogrammed workloads, respectively.
Prefetching, Benchmark testing, Engines, Hardware, Kernel, Linux, Heuristic algorithms
V. Jimenez, R. Gioiosa, F. J. Cazorla, A. Buyuktosunoglu, P. Bose and F. P. O'Connell, "Making data prefetch smarter: Adaptive prefetching on POWER7," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, USA, 2012, pp. 137-146.