2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) (2012)
Minneapolis, MN, USA
Sept. 19, 2012 to Sept. 23, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/
Wim Heirman , ELIS Department, Ghent University, Belgium
Souradip Sarkar , ELIS Department, Ghent University, Belgium
Trevor E. Carlson , ELIS Department, Ghent University, Belgium
Ibrahim Hur , Intel, Leuven, Belgium
Lieven Eeckhout , ELIS Department, Ghent University, Belgium
Stringent performance targets and power constraints push designers towards building specialized workload-optimized systems across a broad spectrum of the computing arena, including supercomputing applications as exemplified by the IBM BlueGene and Intel MIC architectures. In this paper, we make the case for hardware/software co-design during early design stages of processors for scientific computing applications. Considering an important scientific kernel, namely stencil computation, we demonstrate that performance and energy-efficiency can be improved by a factor of 1.66× and 1.25×, respectively, by co-optimizing hardware and software. To enable hardware/software co-design in early stages of the design cycle, we propose a novel simulation infrastructure by combining high-abstraction performance simulation using Sniper with power modeling using McPAT and custom DRAM power models. Sniper/McPAT is fast — simulation speed is around 2 MIPS on an 8-core host machine — because it uses analytical modeling to abstract away core performance during multi-core simulation. We demonstrate Sniper/McPAT's accuracy through validation against real hardware; we report average performance and power prediction errors of 22.1% and 8.3%, respectively, for a set of SPEComp benchmarks.
Computational modeling, Program processors, Analytical models, Hardware, Multicore processing, Random access memory, Integrated circuit modeling
W. Heirman, S. Sarkar, T. E. Carlson, I. Hur and L. Eeckhout, "Power-aware multi-core simulation for early design stage hardware/software co-optimization," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, USA, 2012, pp. 3-12.