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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2011)
Galveston, Texas USA
Oct. 10, 2011 to Oct. 14, 2011
ISSN: 1089-795X
ISBN: 978-0-7695-4566-0
pp: 191-192
ABSTRACT
We propose Proximity-Aware cache Replication (PAR), an LLC replication technique that elegantly integrates an intelligent cache replication placement mechanism and a hierarchical directory-based coherence protocol into one cost-effective and scalable design. Simulation results on a 64-core CMP show that PAR can achieve 12\% speedup over the baseline shared cache design with SPLASH2 and PARSEC workloads. It also provides around 5\% speedup over a couple contemporary approaches with much simpler and scalable support.
INDEX TERMS
Chip multiprocessor, Cache replication, Proximity
CITATION
Chongmin Li, Haixia Wang, Yibo Xue, Dongsheng Wang, Jian Li, "Scalable Proximity-Aware Cache Replication in Chip Multiprocessors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 191-192, 2011, doi:10.1109/PACT.2011.35
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