2011 International Conference on Parallel Architectures and Compilation Techniques (2011)
Galveston, Texas USA
Oct. 10, 2011 to Oct. 14, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2011.35
We propose Proximity-Aware cache Replication (PAR), an LLC replication technique that elegantly integrates an intelligent cache replication placement mechanism and a hierarchical directory-based coherence protocol into one cost-effective and scalable design. Simulation results on a 64-core CMP show that PAR can achieve 12\% speedup over the baseline shared cache design with SPLASH2 and PARSEC workloads. It also provides around 5\% speedup over a couple contemporary approaches with much simpler and scalable support.
Chip multiprocessor, Cache replication, Proximity
D. Wang, C. Li, Y. Xue, J. Li and H. Wang, "Scalable Proximity-Aware Cache Replication in Chip Multiprocessors," 2011 International Conference on Parallel Architectures and Compilation Techniques(PACT), Galveston, Texas USA, 2011, pp. 191-192.