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2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Vienna, Austria
Sept. 11, 2010 to Sept. 15, 2010
ISBN: 978-1-5090-5032-1
pp: 573-574
Rajkishore Barik , Computer Science Department, Rice University, 6100 Main Street, Houston, TX 77005, USA
Jisheng Zhao , Computer Science Department, Rice University, 6100 Main Street, Houston, TX 77005, USA
Vivek Sarkar , Computer Science Department, Rice University, 6100 Main Street, Houston, TX 77005, USA
ABSTRACT
Accelerating program performance via short SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, and AltiVec SIMD instructions in multimedia, scientific, and embedded applications. To take full advantage of the vector capabilities, a compiler needs to generate efficient vector code automatically. However, most commercial and open-source compilers still fall short of using the full potential of vector units, and only generate vector code for simple loop nests. In this poster, we present the design and implementation of an auto-vectorization framework in the back-end of a dynamic compiler that not only generates optimized vector code but is also well integrated with the instruction scheduler and register allocator. Additionally, we describe a vector instruction selection algorithm based on dynamic programming. Our results obtained in JikesRVM dynamic compilation environment show performance improvement of up to 57.71% on an Intel Xeon processor, compared to non-vectorized execution.
INDEX TERMS
Dynamic Optimization, Vectorization, Instruction Selection
CITATION
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar, "Automatic vector instruction selection for dynamic compilation", 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 573-574, 2010, doi:
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