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2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Vienna, Austria
Sept. 11, 2010 to Sept. 15, 2010
ISBN: 978-1-5090-5032-1
pp: 571-572
Shantanu Gupta , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Shuguang Feng , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Amin Ansari , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Ganesh Dasika , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Scott Mahlke , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
ABSTRACT
Single-thread performance, power efficiency and reliability are critical design challenges of future multicore systems. Although point solutions have been proposed to address these issues, a more fundamental change to the fabric of multicore systems is necessary to seamlessly combat these challenges. Towards this end, this paper proposes CoreGenesis, a dynamically adaptive multiprocessor fabric that blurs out individual core boundaries, and encourages resource sharing across cores for performance, reliability and customized processing. Further, as a manifestation of this vision, the paper provides details of a unified performance-reliability solution that can assemble variable-width processors from a network of (potentially broken) pipeline stage-level resources.
INDEX TERMS
Reconfigurable Architectures, Chip Multiprocessors, Fault Tolerance, Configurable Performance
CITATION
Shantanu Gupta, Shuguang Feng, Amin Ansari, Ganesh Dasika, Scott Mahlke, "CoreGenesis: Erasing core boundaries for robust and configurable performance", 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 571-572, 2010, doi:
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