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2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Vienna, Austria
Sept. 11, 2010 to Sept. 15, 2010
ISBN: 978-1-5090-5032-1
pp: 565-566
Ahmed K. Abousamra , University of Pittsburgh, Computer Science Department, PA, USA
Rami G. Melhem , University of Pittsburgh, Computer Science Department, PA, USA
Alex K. Jones , University of Pittsburgh, Electrical and Computer Engineering Department, PA, USA
ABSTRACT
The performance of chip multiprocessors (CMPs) is dependent on the data access latency, which is highly dependent on the design of the on-chip interconnect (NoC) and the organization of the memory caches. However, prior research attempts to optimize the performance of the NoC and cache mostly in isolation of each other. In this work we present a NoC-aware cache design that focuses on communication locality; a property both the cache and NoC affect and can exploit.
INDEX TERMS
CMP, Network-on-chip, NoC, Cache
CITATION
Ahmed K. Abousamra, Rami G. Melhem, Alex K. Jones, "NoC-aware cache design for chip multiprocessors", 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 565-566, 2010, doi:
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