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2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Vienna, Austria
Sept. 11, 2010 to Sept. 15, 2010
ISBN: 978-1-5090-5032-1
pp: 559-560
Haibo Lin , IBM Research - China, Beijing, China
Tong Chen , IBM Watson Research Center, Yorktown Heights, NY, USA
Tao Liu , IBM Research - China, Beijing, China
Lakshminarayanan Renganarayana , IBM Watson Research Center, Yorktown Heights, NY, USA
Huoding Li , IBM Systems & Technology Group, Beijing, China
John Kevin O'Brien , IBM Watson Research Center, Yorktown Heights, NY, USA
ABSTRACT
In this paper we present the design and implementation of a DMATiler which combines compiler analysis and runtime management to optimize local memory performance. In traditional cache model based loop tiling optimizations, the compiler approximates runtime cache misses as the number of distinct cache lines touched by a loop nest. In contrast, the DMATiler has the full control of the addresses, sizes, and sequences of data transfers. DMATiler uses a simplified DMA performance model to formulate the cost model for DMA-tiled loop nests, then solves it using a custom gradient descent algorithm with heuristics guided by DMA characteristics. Given a loop nest, DMATiler uses loop interchange to make the loop order more friendlier for data movements. Moreover, DMATiler applies compressed data buffer and advanced DMA command to further optimize data transfers. We have implemented the DMATiler in the IBM XL C/C++ for Multi-core Acceleration for Linux, and have conducted experiments with a set of loop nest benchmarks. The results show DMATiler is much more efficient than software controlled cache (average speedup of 9.8x) and single level loop blocking (average speedup of 6.2x) on the Cell BE processor.
INDEX TERMS
local memory, Multi-core system, loop tiling
CITATION
Haibo Lin, Tong Chen, Tao Liu, Lakshminarayanan Renganarayana, Huoding Li, John Kevin O'Brien, "DMATiler: Revisiting loop tiling for direct memory access", 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 559-560, 2010, doi:
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