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2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Vienna, Austria
Sept. 11, 2010 to Sept. 15, 2010
ISBN: 978-1-5090-5032-1
pp: 555-556
Rafael Ubal , Dept. of Computing Engineering (DISCA), Universidad Politécnica de Valencia, Camino de Vera, s/n, 46021, Spain
Julio Sahuquillo , Dept. of Computing Engineering (DISCA), Universidad Politécnica de Valencia, Camino de Vera, s/n, 46021, Spain
Salvador Petit , Dept. of Computing Engineering (DISCA), Universidad Politécnica de Valencia, Camino de Vera, s/n, 46021, Spain
Pedro Lopez , Dept. of Computing Engineering (DISCA), Universidad Politécnica de Valencia, Camino de Vera, s/n, 46021, Spain
Jose Duato , Dept. of Computing Engineering (DISCA), Universidad Politécnica de Valencia, Camino de Vera, s/n, 46021, Spain
ABSTRACT
The performance evaluation has been carried out on top of the Multi2Sim 2.2 simulation framework [2], a cycle-accurate simulator for x86-based superscalar processors, extended to model a clustered architecture with support for independent subtraces generation. The parameters of the modeled machine are summarized in Table 1. The Mediabench suite has been used to stress the machine, and simulations are stopped after the first 100 million uops commit. The steering algorithm and the interconnection network among clusters are important design factors related with the criticality of the inter-cluster communication latency. For a good baseline performance, the modeled schemes use a sophisticated steering algorithm called topology-aware steering [3], and several interconnection networks with different realistic link delays are considered.
INDEX TERMS
computer architecture, Clustered processors, subtraces, trace cache
CITATION
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro Lopez, Jose Duato, "Exploiting subtrace-level parallelism in clustered processors", 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 555-556, 2010, doi:
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