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2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Vienna, Austria
Sept. 11, 2010 to Sept. 15, 2010
ISBN: 978-1-5090-5032-1
pp: 453-464
Yangchun Luo , University of Minnesota, Minneapolis, 55455, USA
Venkatesan Packirisamy , NVIDIA Corporation, Santa Clara, CA 95051, USA
Wei-Chung Hsu , National Chiao Tung University, Hsinchu, Taiwan
Antonia Zhai , University of Minnesota, Minneapolis, 55455, USA
ABSTRACT
Thread-level parallelism at the chip level is critical in overcoming some of the challenges that have been ushered in through the advent of modern multicore processors (CMP). Extracting speculatively parallel threads from sequential applications and executing these threads on multicore processors is a promising technique to speed up these applications on multicore systems. However, the potential degradation in energy efficiency associated is an important factor that hinders the deployment of this technique. For multicore systems that integrate same-ISA heterogeneous cores, it is possible to judiciously allocate speculative threads to achieve energy-efficient performance improvement.
INDEX TERMS
Dynamic Resource Allocation, Thread-Level Speculation, Energy Efficiency, Heterogeneous Multicore
CITATION
Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, "Energy efficient speculative threads: Dynamic thread allocation in same-ISA heterogeneous multicore systems", 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 453-464, 2010, doi:
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