Speculative-Aware Execution: A simple and efficient technique for utilizing multi-cores to improve single-thread performance
2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Sept. 11, 2010 to Sept. 15, 2010
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Rania H. Mameesh , Department of Information Engineering, University of Siena, Italy
Manoj Franklin , Department of Electrical and Computer Engineering, College Park, University of Maryland, USA
In this paper a new architecture, Speculative-Aware Execution (SAE) is presented that employs speculative-awareness as a means of mitigating the drawbacks of speculative execution which are: useless work (uses speculative values so it produces incorrect results or is done on the wrong path) and redundant work (produces results previously obtained). In order to achieve this, SAE tries to partition the dynamic instruction stream into two disjoint parallel threads: A speculative thread that is partially speculative-aware (p-thread) as it records its speculative state and uses it to avoid useless work (using speculative values) but have no account for its control-flow violations; and a fully speculative-aware thread (f-thread) that has full record of p-thread's speculations, and so can steer p-thread away from incorrect control-flow paths and can accurately identify p-thread's correct work and avoid it, otherwise it would be redundant. By eliminating useless and redundant works, SAE outperforms existing architectures that share similar high-level micro-architecture while incurring only minor hardware additions/changes. Detailed experimental results confirm that SAE indeed reduces the number of useless and redundant computations. We also report an average performance improvement of 18% for the SPEC_INT2000 benchmarks.
Memory Speculation Bitmap, Speculative aware execution, partially speculative-aware thread, fully speculative-aware thread, Register Speculation Bitmap
R. H. Mameesh and M. Franklin, "Speculative-Aware Execution: A simple and efficient technique for utilizing multi-cores to improve single-thread performance," 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna, Austria, 2010, pp. 421-430.