2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010)
Sept. 11, 2010 to Sept. 15, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/
Victor Jimenez , Barcelona Supercomputing Center Barcelona, Spain
Francisco J. Cazorla , Barcelona Supercomputing Center Barcelona, Spain
Roberto Gioiosa , Barcelona Supercomputing Center Barcelona, Spain
Mateo Valero , Barcelona Supercomputing Center Barcelona, Spain
Carlos Boneti , Schlumberger BRGC, Rio de Janeiro, Brazil
Eren Kursun , IBM T.J. Watson Research Center, Yorktown Heights, USA
Chen-Yong Cher , IBM T.J. Watson Research Center, Yorktown Heights, USA
Canturk Isci , IBM T.J. Watson Research Center, Yorktown Heights, USA
Alper Buyuktosunoglu , IBM T.J. Watson Research Center, Yorktown Heights, USA
Pradip Bose , IBM T.J. Watson Research Center, Yorktown Heights, USA
Controlling power consumption and temperature is of major concern for modern computing systems. In this work we characterize thermal behavior and power consumption of an IBM POWER6™-based system. We perform the characterization at several levels: application, operating system, and hardware level, both when the system is idle, and under load. At hardware level, we report a 25% reduction in total system power consumption by using the processor low power mode. We also study the effect of the hardware thread prioritization mechanism provided by POWER6 on different workloads and how this mechanism can be used to limit power consumption. At OS level, we analyze the power reduction techniques implemented in the Linux kernel, such as the tickless kernel and the CPU idle power manager. At application level, we characterize the power consumption and the temperature of two sets of benchmarks (METbench and SPEC CPU2006) and we study the effect of workload characteristics on power consumption and core temperature. From this characterization we derive a model based on performance counters that allows us to predict the total power consumption of the POWER6 system with an average error under 3% for CMP and 5% for SMT. To the best of our knowledge, this is the first power model of a system including CMP+SMT processors. Finally, we show that the static decision on whether to consolidate tasks into the same core/chip, as it is currently done in Linux, can be improved by dynamically considering the low-power capabilities of the underlying architecture and the characteristics of the application (up to 5X improvement in ED2P).
Performance, Design, Experimentation, Measurement
V. Jimenez et al., "Power and thermal characterization of POWER6 system," 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna, Austria, 2010, pp. 7-18.