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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2009)
Raleigh, North Carolina, USA
Sept. 12, 2009 to Sept. 16, 2009
ISSN: 1089-795X
ISBN: 978-0-7695-3771-9
pp: 227-236
In order to harness the full compute power of many-core processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this paper, we address the dual goals of (1) reducing on-chip communication overheads and (2) improving on-chip cache space utilization resulting in larger effective cache capacity and thereby potentially reduced off-chip traffic. We present a new cache coherence protocol that decouples the logical binding between data and metadata in a cache set. This decoupling allows data and metadata for a cache line to be independently delegated to any location on chip. By delegating metadata to the current owner/modifier of a cache line, communication overhead for metadata maintenance is avoided and communication can be effectively localized between interacting processes. By decoupling metadata from data, data space in the cache can be more efficiently utilized by avoiding unnecessary data replication. Using full system simulation, we demonstrate that our decoupled protocol achieves an average (geometric mean) speedup of 1.24 (1.3 with microbenchmarks) compared to a base statically mapped directory-based non-uniform cache access protocol, while generating only 65% and 74% of the on-chip and off-chip traffic respectively, and consuming 74% of the corresponding energy (95% of the power) in the on-chip memory and interconnect compared to the base system.
Cache Coherence, Chip Multiprocessors, Decoupled Cache, Delegable Cache, DDCache
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang, "DDCache: Decoupled and Delegable Cache Data and Metadata", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 227-236, 2009, doi:10.1109/PACT.2009.24
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