The Community for Technology Leaders
2008 International Conference on Parallel Architectures and Compilation Techniques (PACT) (2008)
Toronto, ON, Canada
Oct. 25, 2008 to Oct. 29, 2008
ISBN: 978-1-5090-3021-7
TABLE OF CONTENTS

Title pages (Abstract)

pp. c1

Outer-loop vectorization - revisited for short SIMD architectures (Abstract)

Dorit Nuzman , IBM Haifa Research Lab, Israel
Ayal Zaks , IBM Haifa Research Lab, Israel
pp. 2-11

Redundancy elimination revisited (Abstract)

Keith Cooper , Dept of Computer Science, Rice University, Houston, TX, USA
Jason Eckhardt , Dept of Computer Science, Rice University, Houston, TX, USA
Ken Kennedy , Dept of Computer Science, Rice University, Houston, TX, USA
pp. 12-21

Exploiting loop-dependent Stream Reuse for stream processors (Abstract)

Xuejun Yang , School of Computer, National University of Defence Technology, ChangSha, China
Ying Zhang , School of Computer, National University of Defence Technology, ChangSha, China
Jingling Xue , The University of New South Wales, Sydney, Australia
Ian Rogers , The University of Manchester, UK
Gen Li , School of Computer, National University of Defence Technology, ChangSha, China
Guibin Wang , School of Computer, National University of Defence Technology, ChangSha, China
pp. 22-31

Feature selection and policy optimization for distributed instruction placement using reinforcement learning (Abstract)

Katherine E. Coons , University of Texas at Austin, USA
Behnam Robatmili , University of Texas at Austin, USA
Matthew E. Taylor , University of Texas at Austin, USA
Betrand A. Maher , University of Texas at Austin, USA
Doug Burger , University of Texas at Austin, USA
Kathryn S. McKinley , University of Texas at Austin, USA
pp. 32-42

Core Cannibalization Architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults (Abstract)

Bogdan F. Romanescu , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Daniel J. Sorin , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
pp. 43-51

Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor (Abstract)

Henry Wong , Dept. of Electrical and Computer Engineering, University of British Columbia, Canada
Anne Bracy , Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation, USA
Ethan Schuchman , Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation, USA
Tor M. Aamodt , Dept. of Electrical and Computer Engineering, University of British Columbia, Canada
Jamison D. Collins , Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation, USA
Perry H. Wang , Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation, USA
Gautham Chinya , Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation, USA
Ankur Khandelwal Groen , Digital Enterprise Group, Intel Corporation, USA
Hong Jiang , Graphics Architecture, Mobility Groups, Intel Corporation, USA
Hong Wang , Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation, USA
pp. 52-61

Skewed redundancy (Abstract)

Gordon B. Bell , IBM Corporation, Research Triangle Park, NC, USA
Mikko H. Lipasti , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
pp. 62-71

The PARSEC benchmark suite: Characterization and architectural implications (Abstract)

Christian Bienia , Department of Computer Science, Princeton University, USA
Sanjeev Kumar , Microprocessor Technology Labs, Intel, USA
Jaswinder Pal Singh , Department of Computer Science, Princeton University, USA
Kai Li , Department of Computer Science, Princeton University, USA
pp. 72-81

Visualizing potential parallelism in sequential programs (Abstract)

Graham D. Price , University of Colorado at Boulder, USA
John Giacomoni , University of Colorado at Boulder, USA
Manish Vachharajani , University of Colorado at Boulder, USA
pp. 82-90

Characterizing and modeling the behavior of context switch misses! (Abstract)

Fang Liu , Dept. of Electrical and Computer Engineering, NC State University, USA
Fei Guo , Dept. of Electrical and Computer Engineering, NC State University, USA
Yan Solihin , Dept. of Electrical and Computer Engineering, NC State University, USA
Seongbeom Kim , VMWare Inc., USA
Abdulaziz Eker , Scientific and Technological Research Council, Ankara, Turkey
pp. 91-101

MCAMP: Communication optimization on Massively Parallel Machines with hierarchical scratch-pad memory (Abstract)

Hiroshige Hayashizaki , Graduate School of Information Science and Technology, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Japan
Yutaka Sugawara , Graduate School of Information Science and Technology, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Japan
Mary Inaba , Graduate School of Information Science and Technology, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Japan
Kei Hiraki , Graduate School of Information Science and Technology, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Japan
pp. 102-111

Profiler and compiler assisted adaptive I/O prefetching for shared storage caches (Abstract)

Seung Woo Son , Pennsylvania State University, USA
Sai Prashanth Muralidhara , Pennsylvania State University, USA
Ozcan Ozturk , Bilkent University, Turkey
Mahmut Kandemir , Pennsylvania State University, USA
Ibrahim Kolcu , University of Manchester, UK
Mustafa Karakoy , Imperial College, USA
pp. 112-121

Runtime optimization of vector operations on large scale SMP clusters (Abstract)

Costin Iancu , Lawrence Berkeley National Laboratory, CA, USA
Steven Hofmeyr , Lawrence Berkeley National Laboratory, CA, USA
pp. 122-132

(How) can programmers conquer the multicore menace? (Abstract)

Saman Amarasinghe , Massachusetts Institute of Technology, MA, USA
pp. 133

Distributed Cooperative Caching (Abstract)

Enric Herrero , Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Spain
Jose Gonzalez , Intel Barcelona Research Center, Intel Labs-Universitat, Politècnica de Catalunya, Spain
Ramon Canal , Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Spain
pp. 134-143

Scalable and reliable communication for hardware transactional memory (Abstract)

Seth H. Pugsley , School of Computing, University of Utah, USA
Manu Awasthi , School of Computing, University of Utah, USA
Niti Madan , School of Computing, University of Utah, USA
Naveen Muralimanohar , School of Computing, University of Utah, USA
Rajeev Balasubramonian , School of Computing, University of Utah, USA
pp. 144-154

Improving support for locality and fine-grain sharing in chip multiprocessors (Abstract)

Hemayet Hossain , University of Rochester, USA
Sandhya Dwarkadas , University of Rochester, USA
Michael C. Huang , University of Rochester, USA
pp. 155-165

Edge-centric modulo scheduling for coarse-grained reconfigurable architectures (Abstract)

Hyunchul Park , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA
Kevin Fan , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA
Scott Mahlke , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA
Taewook Oh , Samsung Advanced Institute of Technology, Kiheung, Republic of Korea
Heeseok Kim , Samsung Advanced Institute of Technology, Kiheung, Republic of Korea
Hong-seok Kim , Samsung Advanced Institute of Technology, Kiheung, Republic of Korea
pp. 166-176

Multi-Optimization power management for chip multiprocessors (Abstract)

Ke Meng , EECS Department, Northwestern University, Evanston, IL, USA
Russ Joseph , EECS Department, Northwestern University, Evanston, IL, USA
Robert P. Dick , EECS Department, Northwestern University, Evanston, IL, USA
Li Shang , ECE Department, University of Colorado, Boulder, USA
pp. 177-186

Multitasking workload scheduling on flexible-core chip multiprocessors (Abstract)

Divya P. Gulati , University of Texas at Austin, 1 University Station C0500, 78712, USA
Changkyu Kim , Intel Corporation, 3600 Juliette Ln, SC12-303, Santa Clara, California 95054, USA
Simha Sethumadhavan , Columbia University, 1214 Amsterdam Ave., New York, 10027, USA
Stephen W. Keckler , University of Texas at Austin, 1 University Station C0500, 78712, USA
Doug Burger , University of Texas at Austin, 1 University Station C0500, 78712, USA
pp. 187-196

Leveraging on-chip networks for data cache migration in chip multiprocessors (Abstract)

Noel Eisley , Dept. of EE, Princeton University, NJ 08544, USA
Li-Shiuan Peh , Dept. of EE, Princeton University, NJ 08544, USA
Li Shang , Dept. of ECE, University of Colorado, Boulder, 80309, USA
pp. 197-207

Adaptive insertion policies for managing shared caches (Abstract)

Aamer Jaleel , Intel Corporation, VSSAD, Hudson, MA, USA
William Hasenplaugh , Intel Corporation, VSSAD, Hudson, MA, USA
Moinuddin Qureshi , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Julien Sebot , Intel Israel Design Center, Haifa, Israel
Simon Steely , Intel Corporation, VSSAD, Hudson, MA, USA
Joel Emer , Intel Corporation, VSSAD, Hudson, MA, USA
pp. 208-219

Analysis and approximation of optimal co-scheduling on Chip Multiprocessors (Abstract)

Yunlian Jiang , Computer Science Department, College of William and Mary, VA, USA
Xipeng Shen , Computer Science Department, College of William and Mary, VA, USA
Chen Jie , Scientific Computing Group, Thomas Jefferson National Accelerator Facility, VA, USA
Rahul Tripathi , Computer Science Department, University of South Florida, USA
pp. 220-229

An Adaptive Resource Partitioning Algorithm for SMT processors (Abstract)

Huaping Wang , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
Israel Koren , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
C. Mani Krishna , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
pp. 230-239

Meeting points: Using thread criticality to adapt multicore hardware to parallel regions (Abstract)

Qiong Cai , Intel Barcelona Research Center, Intel Labs-UPC, Spain
Jose Gonzalez , Intel Barcelona Research Center, Intel Labs-UPC, Spain
Ryan Rakvic , United States Naval Academy, Annapolis, Maryland, USA
Grigorios Magklis , Intel Barcelona Research Center, Intel Labs-UPC, Spain
Pedro Chaparro , Intel Barcelona Research Center, Intel Labs-UPC, Spain
Antonio Gonzalez , Intel Barcelona Research Center, Intel Labs-UPC, Spain
pp. 240-249

Prediction models for multi-dimensional power-performance optimization on many cores (Abstract)

Matthew Curtis-Maury , Dept. of Computer Science, Virginia Tech, Blacksburg, USA
Ankur Shah , Dept. of Computer Science, Virginia Tech, Blacksburg, USA
Filip Blagojevic , Dept. of Computer Science, Virginia Tech, Blacksburg, USA
Dimitrios S. Nikolopoulos , Dept. of Computer Science, Virginia Tech, Blacksburg, USA
Bronis R. de Supinski , Lawrence Livermore National Laboratory, CA, USA
Martin Schulz , Lawrence Livermore National Laboratory, CA, USA
pp. 250-259

Mars: A MapReduce Framework on graphics processors (Abstract)

Bingsheng He , HKUST, China
Wenbin Fang , HKUST, China
Qiong Luo , HKUST, China
Naga K. Govindaraju , Microsoft Corp., USA
Tuyong Wang , Sina Corp., China
pp. 260-269

Multi-mode energy management for multi-tier server clusters (Abstract)

Tibor Horvath , Department of Computer Science, University of Virginia, Charlottesville, 22904, USA
Kevin Skadron , Department of Computer Science, University of Virginia, Charlottesville, 22904, USA
pp. 270-279

A tuning framework for software-managed memory hierarchies (Abstract)

Manman Ren , Stanford University, USA
Ji Young Park , Stanford University, USA
Mike Houston , Stanford University, USA
Alex Aiken , Stanford University, USA
William J. Dally , Stanford University, USA
pp. 280-291

Hybrid access-specific software cache techniques for the cell BE architecture (Abstract)

Marc Gonzalez , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Nikola Vujic , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Xavier Martorell , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Eduard Ayguade , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Alexandre E. Eichenberger , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Tong Chen , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Zehra Sura , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Tao Zhang , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Kevin O'Brien , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Kathryn O'Brien , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
pp. 292-302

COMIC: A coherent shared memory interface for cell BE (Abstract)

Jaejin Lee , School of Computer Science and Engineering, Seoul National University, Korea
Sangmin Seo , School of Computer Science and Engineering, Seoul National University, Korea
Chihun Kim , School of Computer Science and Engineering, Seoul National University, Korea
Junghyun Kim , School of Computer Science and Engineering, Seoul National University, Korea
Posung Chun , School of Computer Science and Engineering, Seoul National University, Korea
Zehra Sura , IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA
Jungwon Kim , School of Computer Science and Engineering, Seoul National University, Korea
SangYong Han , School of Computer Science and Engineering, Seoul National University, Korea
pp. 303-314

Author index (PDF)

pp. 315
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