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2008 International Conference on Parallel Architectures and Compilation Techniques (PACT) (2008)
Toronto, ON, Canada
Oct. 25, 2008 to Oct. 29, 2008
ISBN: 978-1-5090-3021-7
pp: 292-302
Marc Gonzalez , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Nikola Vujic , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Xavier Martorell , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Eduard Ayguade , Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
Alexandre E. Eichenberger , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Tong Chen , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Zehra Sura , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Tao Zhang , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Kevin O'Brien , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
Kathryn O'Brien , IBM T.J. Watson Research Center, Yorktown Heights, New York, USA
ABSTRACT
Ease of programming is one of the main impediments for the broad acceptance of multi-core systems with no hardware support for transparent data transfer between local and global memories. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this paper, we propose a hierarchical, hybrid software-cache architecture that classifies at compile time memory accesses in two classes, high-locality and irregular. Our approach then steers the memory references toward one of two specific cache structures optimized for their respective access pattern. The specific cache structures are optimized to enable high-level compiler optimizations to aggressively unroll loops, reorder cache references, and/or transform surrounding loops so as to practically eliminate the software cache overhead in the innermost loop. Performance evaluation indicates that improvements due to the optimized software-cache structures combined with the proposed code-optimizations translate into 3.5 to 8.4 speedup factors, compared to a traditional software cache approach. As a result, we demonstrate that the Cell BE processor can be a competitive alternative to a modern server-class multi-core such as the IBM Power5 processor for a set of parallel NAS applications.
INDEX TERMS
Software, Computer architecture, Optimization, Cache storage, Synchronization, Radiation detectors, Hardware,software cache, OpenMP, compiler optimizations, local memories, memory classification
CITATION
Marc Gonzalez, Nikola Vujic, Xavier Martorell, Eduard Ayguade, Alexandre E. Eichenberger, Tong Chen, Zehra Sura, Tao Zhang, Kevin O'Brien, Kathryn O'Brien, "Hybrid access-specific software cache techniques for the cell BE architecture", 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 292-302, 2008, doi:
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