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2008 International Conference on Parallel Architectures and Compilation Techniques (PACT) (2008)
Toronto, ON, Canada
Oct. 25, 2008 to Oct. 29, 2008
ISBN: 978-1-5090-3021-7
pp: 72-81
Christian Bienia , Department of Computer Science, Princeton University, USA
Sanjeev Kumar , Microprocessor Technology Labs, Intel, USA
Jaswinder Pal Singh , Department of Computer Science, Princeton University, USA
Kai Li , Department of Computer Science, Princeton University, USA
ABSTRACT
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Previous available benchmarks for multiprocessors have focused on high-performance computing applications and used a limited number of synchronization methods. PARSEC includes emerging applications in recognition, mining and synthesis (RMS) as well as systems applications which mimic large-scale multithreaded commercial programs. Our characterization shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic. The benchmark suite has been made available to the public.
INDEX TERMS
Benchmark testing, Computational modeling, Synchronization, Animation, Computers, Algorithm design and analysis, Program processors
CITATION
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li, "The PARSEC benchmark suite: Characterization and architectural implications", 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 72-81, 2008, doi:
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