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2008 International Conference on Parallel Architectures and Compilation Techniques (PACT) (2008)
Toronto, ON, Canada
Oct. 25, 2008 to Oct. 29, 2008
ISBN: 978-1-5090-3021-7
pp: 43-51
Bogdan F. Romanescu , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Daniel J. Sorin , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
ABSTRACT
To improve the lifetime performance of a multicore chip with simple cores, we propose the Core Cannibalization Architecture (CCA). A chip with CCA provisions a fraction of the cores as cannibalizable cores (CCs). In the absence of hard faults, the CCs function just like normal cores. In the presence of hard faults, the CCs can be cannibalized for spare parts at the granularity of pipeline stages. We have designed and laid out CCA chips composed of multiple OpenRISC 1200 cores. Our results show that CCA improves the chips' lifetime performances, compared to chips without CCA.
INDEX TERMS
Multicore processing, Program processors, Circuit faults, Pipelines, Registers, Wires, Layout
CITATION
Bogdan F. Romanescu, Daniel J. Sorin, "Core Cannibalization Architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults", 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), vol. 00, no. , pp. 43-51, 2008, doi:
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