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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Brasov, Romania
Sept. 15, 2007 to Sept. 19, 2007
ISSN: 1089-795X
ISBN: 0-7695-2944-5
pp: 433
Jing Yu , University of Illinois at Urbana-Champaign, USA
Maria Jesus Garzaran , University of Illinois at Urbana-Champaign, USA
ABSTRACT
Dramatic increases in the number of transistors that can be integrated on a chip will make the hardware more susceptible to radiation-induced transient errors. Highend architectures like the IBM mainframes, HP NonStop or mission-critical computers are likely to include several hardware-intensive fault tolerance techniques. However, the commodity chips which are cost- and energy-constrained, will need a more flexible and inexpensive technology for error detection. Software approaches can play a major role for this sector of the market because they need little hardware modification and can be tailored to fit different requirements of reliability and performance.
INDEX TERMS
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CITATION
Jing Yu, Maria Jesus Garzaran, "Compiler Optimizations for Fault Tolerance Software Checking", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 433, 2007, doi:10.1109/PACT.2007.22
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