16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.22
Jing Yu , University of Illinois at Urbana-Champaign, USA
Maria Jesus Garzaran , University of Illinois at Urbana-Champaign, USA
Dramatic increases in the number of transistors that can be integrated on a chip will make the hardware more susceptible to radiation-induced transient errors. Highend architectures like the IBM mainframes, HP NonStop or mission-critical computers are likely to include several hardware-intensive fault tolerance techniques. However, the commodity chips which are cost- and energy-constrained, will need a more flexible and inexpensive technology for error detection. Software approaches can play a major role for this sector of the market because they need little hardware modification and can be tailored to fit different requirements of reliability and performance.
J. Yu and M. J. Garzaran, "Compiler Optimizations for Fault Tolerance Software Checking," 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(PACT), Brasov, Romania, 2007, pp. 433.