16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.13
Philip M. Wells , University of Wisconsin, Madison, USA
Koushik Chakraborty , University of Wisconsin, Madison, USA
Gurindar S. Sohi , University of Wisconsin, Madison, USA
As technology continues to scale, future multicore processors become more susceptible to a variety of hardware failures. In particular, intermittent faults, are expected to become especially problematic [1, 2]. A circuit is susceptible to intermittent faults when manufacturing process variation or in-progress wear-out causes the parameters (e.g., resistance, threshold voltage, etc.) of devices within the circuit to vary beyond design expectations . This susceptibility, combined with certain operating conditions, such as thermal hot-spots and voltage fluctuations, can result in timing errors--even if these temperatures and voltages, for example, are well within the specified "acceptable" margins.
K. Chakraborty, G. S. Sohi and P. M. Wells, "Adapting to Intermittent Faults in Future Multicore Systems," 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(PACT), Brasov, Romania, 2007, pp. 431.