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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Brasov, Romania
Sept. 15, 2007 to Sept. 19, 2007
ISSN: 1089-795X
ISBN: 0-7695-2944-5
pp: 429
P. Lopez , Universidad Politecnica de Valencia, Spain
J. Sahuquillo , Universidad Politecnica de Valencia, Spain
S. Petit , Universidad Politecnica de Valencia, Spain
R. Ubal , Universidad Politecnica de Valencia, Spain
J. Duato , Universidad Politecnica de Valencia, Spain
ABSTRACT
The Validation Buffer (VB) Microarchitecture [4] retires instructions out of order, by substituting the classical ROB by the VB structure. The VB removes the negative effect of long latency instructions located at the ROB head, which prevent other instructions from retiring and cause frequent pipeline stalls due to lack of space in the ROB.
INDEX TERMS
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CITATION
P. Lopez, J. Sahuquillo, S. Petit, R. Ubal, J. Duato, "VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 429, 2007, doi:10.1109/PACT.2007.78
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