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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Brasov, Romania
Sept. 15, 2007 to Sept. 19, 2007
ISSN: 1089-795X
ISBN: 0-7695-2944-5
pp: 427
Hiroaki Shikano , Waseda University, Japan; Hitachi, Ltd., Japan
Jun Shirako , Waseda University, Japan
Yasutaka Wada , Waseda University, Japan
Keiji Kimura , Waseda University, Japan
Hironori Kasahara , Waseda University, Japan
ABSTRACT
Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation with the OSCAR (Optimally SCheduled Advanced multiprocessoR) parallelizing compiler[1].
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CITATION
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 427, 2007, doi:10.1109/PACT.2007.54
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