16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.54
Hiroaki Shikano , Waseda University, Japan; Hitachi, Ltd., Japan
Jun Shirako , Waseda University, Japan
Yasutaka Wada , Waseda University, Japan
Keiji Kimura , Waseda University, Japan
Hironori Kasahara , Waseda University, Japan
Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation with the OSCAR (Optimally SCheduled Advanced multiprocessoR) parallelizing compiler.
J. Shirako, K. Kimura, H. Shikano, H. Kasahara and Y. Wada, "Power-Aware Compiler Controllable Chip Multiprocessor," 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(PACT), Brasov, Romania, 2007, pp. 427.