Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.27
Kaushik Rajan , Indian Institute of Science, India
R. Govindarajan , Indian Institute of Science, India
Bharadwaj Amrutur , Indian Institute of Science, India
Due to the tight coupling between processor cycle time and L1 access time, L1 caches are typically small and have low associativities. As a consequence they incur a higher percentage of conflict misses than lower level caches. The extent of conflict depends on the memory access pattern exhibited by the program, and can vary from program to program. By using a fixed set of bits to index the cache, conventional mapping enforces the same rigid mapping from address to cache set for all programs. This results in a nonuniform distribution of addresses among cache sets causing unnecessary conflict misses. Such conflicts could be avoided if some flexibility in mapping is exercised.
Kaushik Rajan , R. Govindarajan, Bharadwaj Amrutur, "Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 422, 2007, doi:10.1109/PACT.2007.27