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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Brasov, Romania
Sept. 15, 2007 to Sept. 19, 2007
ISSN: 1089-795X
ISBN: 0-7695-2944-5
pp: 418
Miquel Moreto , Universitat Politecnica de Catalunya, Spain
Francisco J. Cazorla , Universitat Politecnica de Catalunya, Spain
Alex Ramirez , Universitat Politecnica de Catalunya, Spain; Barcelona Supercomputing Center, Spain
Mateo Valero , Universitat Politecnica de Catalunya, Spain; Barcelona Supercomputing Center, Spain
ABSTRACT
The limitation imposed by instruction-level parallelism (ILP) has motivated the use of thread-level parallelism (TLP) as a common strategy for improving processor performance. TLP paradigms such as simultaneous multithreading (SMT), chip multiprocessing (CMP) and combinations of both offer the opportunity to obtain higher throughputs. However, they also have to face the challenge of sharing resources of the architecture. Simply avoiding any resource control can lead to undesired situations where one thread is monopolizing all the resources and harming the other threads. Some studies deal with the resource sharing problem in SMTs at core level resources like issue queues, registers, etc. In CMPs, resource sharing is lower than in SMT, focusing in the cache hierarchy.
INDEX TERMS
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CITATION
Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, "MLP-Aware Dynamic Cache Partitioning", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 418, 2007, doi:10.1109/PACT.2007.49
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