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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Brasov, Romania
Sept. 15, 2007 to Sept. 19, 2007
ISSN: 1089-795X
ISBN: 0-7695-2944-5
pp: 416
Steve Dropsho , EPFL, Switzerland
Sonia Lopez , Universidad Comlutense de Madrid, Spain
Juan Lanchares , Universidad Comlutense de Madrid, Spain
Oscar Garnica , Universidad Comlutense de Madrid, Spain
David H. Albonesi , Cornell University, USA
ABSTRACT
Resizable caches can tradeoff capacity for access speed to dynamically match the needs of the workload. In single-threaded cores, resizable caches adapt to the phases of the running application. In Simultaneous Multi- Threaded (SMT) cores the caching needs can vary greatly across the number of threads and their characteristics, thus, offering even more opportunities to dynamically adjust cache resources to the workload.
INDEX TERMS
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CITATION
Steve Dropsho, Sonia Lopez, Juan Lanchares, Oscar Garnica, David H. Albonesi, "Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 416, 2007, doi:10.1109/PACT.2007.56
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