16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.56
Sonia Lopez , Universidad Comlutense de Madrid, Spain
Steve Dropsho , EPFL, Switzerland
David H. Albonesi , Cornell University, USA
Oscar Garnica , Universidad Comlutense de Madrid, Spain
Juan Lanchares , Universidad Comlutense de Madrid, Spain
Resizable caches can tradeoff capacity for access speed to dynamically match the needs of the workload. In single-threaded cores, resizable caches adapt to the phases of the running application. In Simultaneous Multi- Threaded (SMT) cores the caching needs can vary greatly across the number of threads and their characteristics, thus, offering even more opportunities to dynamically adjust cache resources to the workload.
S. Dropsho, S. Lopez, J. Lanchares, O. Garnica and D. H. Albonesi, "Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors," 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(PACT), Brasov, Romania, 2007, pp. 416.