16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.70
Stijn Eyerman , Ghent University, Belgium
Lieven Eeckhout , Ghent University, Belgium
James E. Smith , University of Wisconsin-Madison, USA
In modern processors, both the hardware implementation and optimizing compilers are very complex, and they often interact in unpredictable ways. A high performance microarchitecture typically issues instructions out-of-order and must deal with a number of disruptive miss events such as branch mispredictions and cache misses. An optimizing compiler implements a large number of individual optimizations which not only interact with the microarchitecture, but also interact with each other. These interactions can be constructive, destructive, or neutral. Furthermore, whether there is performance gain or loss often depends on the particular program being optimized and executed.
S. Eyerman, L. Eeckhout and J. E. Smith, "Studying Compiler-Microarchitecture Interactions through Interval Analysis," 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(PACT), Brasov, Romania, 2007, pp. 406.