16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (2007)
Sept. 15, 2007 to Sept. 19, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2007.46
Xiaofeng Guo , Google Inc
Jinquan Dai , Intel China Software Center, China
Long Li , Intel China Software Center, China
Zhiyuan Lv , Intel China Software Center, China
Prashant R. Chandra , Intel Corporation
Network processors employ a multithreaded, chip-multiprocessing architecture to effectively hide memory latency and deliver high performance for packet processing applications. In such a parallel paradigm, when multiple threads modify a shared variable in the external memory, the threads should be properly synchronized such that the accesses to the shared variable are protected by critical sections. Therefore, in order to efficiently harness the performance potential of network processors, it is critical to hide the memory latency and synchronization latency in multi-threading and multiprocessing. In this paper, we present a novel program transformation used in the Intel? Auto-partitioning C Compiler for IXP, which perform optimal placement of memory access instructions and synchronization instructions for effective latency hiding. Experimental results show that the transformation provides impressive speedup (up-to to 8.5x) and scalability (upto 72 threads) of the performance for the real-world network application (a 10Gbps Ethernet Core/Metro Router).
J. Dai, X. Guo, Z. Lv, P. R. Chandra and L. Li, "Latency Hiding in Multi-Threading and Multi-Processing of Network Applications," 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(PACT), Brasov, Romania, 2007, pp. 270-279.