The Community for Technology Leaders
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2007)
Brasov, Romania
Sept. 15, 2007 to Sept. 19, 2007
ISSN: 1089-795X
ISBN: 0-7695-2944-5
pp: 60-72
Suhyun Kim , IBM T.J. Watson Research Center, USA
Soo-Mook Moon , Seoul National University, Korea
ABSTRACT
A rotating register file is a compiler-managed hardware renaming mechanism for overcoming the cross-iteration register overwrite problem in software pipelining [3]. It has primarily been used for software pipelining of straight-line and if-converted loops in the context of modulo scheduling. This paper proposes using rotating registers for software pipelining of loops with arbitrary control flows, in the context of enhanced pipeline scheduling (EPS). EPS can achieve a tight, variable initiation interval for such loops, but generates many hard-to-delete copies for handling the cross-iteration register overwrite problem. These copies may cause a stall if they renamed multi-latency instructions, in addition to taking resources. In the prior work [9], these copies were removed by loop unrolling using an abstraction called extended live range (ELR). In this paper, we eliminate those copies by allocating rotating registers using the same ELR yet with a different interpretation, since both techniques share a similar intuition for copy elimination. There are some differences in building and using ELRs, though, which will also be discussed. We also discuss how existing rotating register allocation techniques cannot be easily adapted for EPS to handle loops with control flows. Our experimental results indicate that we can eliminate 50% of otherwise uncoalescible copies via rotating register allocation, which allows us to avoid a serious slowdown from latency handling and resource pressure without code expansion as in unrolling.
INDEX TERMS
null
CITATION
Suhyun Kim, Soo-Mook Moon, "Rotating Register Allocation for Enhanced Pipeline Scheduling", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 60-72, 2007, doi:10.1109/PACT.2007.61
102 ms
(Ver 3.3 (11022016))